1. Field of the Invention
This application pertains generally to data communication systems and more specifically to the field of clock recovery in multi-carrier systems.
2. Description of the Background Art
A multi carrier transmission system is one that employs frequency division multiplexed (FDM) sub-carriers for transmission. A comprehensive description of multicarrier systems is given by John A. C. Bingham in xe2x80x9cMulticarrier Modulation for Data Transmission: An idea whose time has comexe2x80x9d, IEEE Communication Magazine, Vol. 28, No. 5, pp. 5-14, May 1990.
In conventional communication systems a receiver has to perform clock and carrier recovery. However typical multicarrier systems use lookup tables for generating individual carriers through a sample clock. As a result carrier frequencies are dependent on the clock frequency. Therefore independent carrier frequency recovery is not required.
Clock recovery is the problem of synchronizing a receiver""s clock to that of the transmitter. The problem of clock recovery is however made complicated by the presence of channel noise, frequency offset, clock drift and phase jitter. Channel noise comprises thermal noise and noise induced due to other similar systems existing in that environment. Frequency offset can arise due to other communication equipment present in the channel. These equipment in modulation and subsequent demodulation may shift the signal spectrum, as described by John A. C. Bingham in xe2x80x9cMethod and Apparatus for Correcting for Clock and Carrier Frequency Offset and Phase Jitter in Multicarrier Modemsxe2x80x9d, U.S. Pat. No. 5,228,062, herein incorporated by reference, and issued Jul. 13, 1993. Clock drift is caused by crystal imperfections and temperature variations. Phase jitter is mainly attributed to power line coupling, however phase jitter can also arise from crystal imperfections and other circuit limitations. Any clock recovery circuit has to therefore estimate these parameters and then track them in the presence of frequency offset, clock drift and phase jitter.
In the past many schemes have been suggested for addressing the above problems. Almost all of these techniques are based on the use of phase locked loops (PLLs). These schemes work well in general, however the loop filters need to be designed carefully to provide the required performance. In multicarrier systems the symbol periods are typically large and corresponding PLL delays would also be large, making the tracking problem difficult.
The clock recovery problem in multicarrier systems has been addressed by U.S. Pat. No. 5,228,062 issued Jul. 13, 1993. In this method, a combination of block and serial processing techniques have been proposed for compensating offset and jitter. These schemes use a plurality of pilot tones during an initial training mode for estimation of clock error, frequency offset and phase jitter components. The training mode is followed by a data mode, during which the actual data is encoded into symbols (referred to as data mode symbols here in after) and transmitted through the channel. In data mode, the clock error due to clock drift, frequency offset and phase jitter estimates are updated using data mode symbols. This scheme and its limitations are described below.
The clock error estimation is done by first fitting a straight line to the phase error profile of the received symbols. The straight line fit is typically carried out in a linear least square sense, where the parameters of the straight line are found in such a way that the square of the error between the resulting straight line and the phase error profile is minimum. The slope of the linear fit is then passed through a low pass filter designed using conventional PLL theory to obtain a correction for the clock circuit. This scheme however is limited in performance due to two main reasons:
a) The linear least squares estimation carried out is sub-optimal when the noise in the phase samples is coloured. Noise colouring is relevant in some applications of multicarrier systems, such as those that work in an Asymmetric Digital Subscriber Line (ADSL) environment. In this environment noise resulting from other loops in the same binder is coloured and moreover is a dominant component of the total received noise. Further description of the noise in an ADSL environment can be found in ANSI T1.413-1998, American National Standard for Telecommunicationsxe2x80x94Network and Customer Installation Interfacesxe2x80x94Asymmetric Digital Subscriber Line (ADSL) Metallic Interface, 1998.
b) The clock recovery and tracking proposed in many conventional systems involve sending a frequency correction to the receiver clock. The correction can be incorporated through a change in the receiver clock or by carrying out interpolation of received samples. Typically a voltage controlled oscillator (VCXO) is controlled through this correction to change the receiver clock. It is customary to provide the VCXO input through a digital to analog converter (DAC) the input to which is the correction value provided as a discrete number. These systems are limited in their ability to provide a continuous range of clock frequencies (since the frequency correction resolution is determined by the smallest non-zero quantity the DAC can output), resulting in a non-zero residual error within the least count of the system. Such an error unless explicitly randomized will manifest as a biased phase error and eventually lead to loss in synchronization and failure. Typical implementations do not address this problem as estimation errors due to system noise and clock jitter provides some degree of randomization.
The measurement of clock error can also be carried out using the scheme proposed by G. Ungerboeck, xe2x80x9cFractional Tap-Spacing Equalizer and Consequences for Clock Recovery in Data Modemsxe2x80x9d, IEEE Tr. Communications, COM-24, No. 8, pp. 856-864, August, 1976. This scheme uses a measure of the drift in the taps of a time domain equalizer to get an estimate of the frequency correction. It is particularly suited for communication receivers that utilize adaptive equalizers. However these schemes cannot be directly applied to high data rate multicarrier systems, as the updation of time domain equalizer taps is computationally expensive.
This invention proposes a novel scheme for clock synchronization in multicarrier systems which addresses the limitations described above, including the effect of channel noise and clock drift on the synchronization problem. The effect of frequency offset and phase jitter is not explored in this invention. However those skilled in the art can combine conventional frequency offset and phase jitter solutions with the novel scheme proposed in this invention for a complete clock recovery.
The proposed scheme also provides two additional features. The first is an optimal method for determining the acquisition time, which is used for reducing the training time. The second is a procedure for optimal tracking of non-stationarity arising out of clock drift.
In accordance with the present invention, an optimal estimate of clock frequency error between the transmitter and receiver using a pilot signal and the statistics of the noise process is computed during a training mode. In a preferred embodiment, the estimate is such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. The present invention also provides for optimal estimates for systems in which colored noise is introduced, for example, in an ADSL environment. Further, a tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism preferably involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean.
A multicarrier system which consists of a training phase preceding a data transmission phase is provided. The training phase includes a transmission of a known signal in a particular sub-carrier referred to as a pilot channel. This is used to obtain an optimal estimate of the error between the transmitter and receiver clocks in the following way:
1) Determination of the discrete Fourier transform coefficients of the pilot channel which are used to a) obtain the signal to noise ratio (SNR) in the channel and b) obtain the autocorrelation statistics of the noise process.
2) Design of a minimum variance unbiased estimator filter using the SNR, noise autocorrelation statistics and predefined estimation error which could for example be based on the least count of the system that controls the sample clock. This ensures that the filter designed is optimal in the number of samples required for a given noise statistics and estimation error. Alternately, it provides an estimate with minimum variance for a given number of samples and noise statistics. This filter is used for determination of the clock error estimate that is sent as a correction to the receiver clock.
The training phase may also involve determination of the following: a) parameters of the phase jitter and frequency offset components in the system which can be done using techniques described in by U.S. Pat. No. 5,228,062, b) taps of a frequency domain equalizer for compensating the channel characteristics.
The initial estimate is then refined during data mode in the following way:
1) The frequency domain equalizer taps are adapted using a least mean squares (LMS) algorithm using the decoded output as a reference signal. A measure of the drift in these taps is used to obtain an estimate of the residual clock error.
2) If the pilot signal is continued in the data mode, then the scheme deployed during training mode is used to obtain another estimate of the residual clock error.
3) The error estimates obtained in the above steps are combined to obtain a possible clock correction.
4) The correction obtained is input to a dithering algorithm to obtain the actual correction. The dithering algorithm ensures that the phase error does not build up beyond manageable proportions whenever the clock error is below the least count.
The filter is optimal in the number of samples it uses for determination of estimate. This can be used to terminate clock recovery faster than existing schemes, allowing for shorter training times. Conventional phase jitter and frequency offset tracking mechanisms can also be easily combined with the above optimal clock recovery mechanism.
In data mode, a tracking scheme that makes uses of variations in frequency domain equalizer taps for determination of residual clock error estimate, different from the error estimate generation method used in the training mode is disclosed. A SNR based combination of errors is computed to obtain an estimated residual clock correction value. A dithering mechanism computes the actual correction to be given to the VCXO such that the residual phase error is maintained at an acceptably low value.